The present invention relates to digital computer systems, and more particularly, to digital data compression and decompression schemes employed in digital computer systems.
Digital computer systems perform data compression to realize a more efficient use of finite storage space. The computer system typically includes a hardware component referred to as an accelerator, which accepts work requests or data requests from the host system to compress or decompress one or more blocks of the requested data. When designing an accelerator to perform compression, there is a tradeoff between the size of the input data that is to be compressed compared to the possible compression ratio and the latency that results from compressing the data.